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TPD4E6B06 Datasheet(PDF) 11 Page - Texas Instruments |
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TPD4E6B06 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 15 page = VIA 1 4 3 2 GND = VIA to GND Plane 1 4 3 2 TPD4E6B06 www.ti.com SLVSCK3A – MAY 2014 – REVISED DECEMBER 2015 9 Layout 9.1 Layout Guidelines • Place the device as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer should minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. • Route the protected traces as straight as possible. • Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 9.2 Layout Examples Figure 12. Single Layer Routing Figure 13. Double Layer Routing Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPD4E6B06 |
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