Unused Input

Input

Output

Input

Unused Input

Output

0

1

2

3

4

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

D003

VOUT input low

VOUT input high

10

SN54LV06A, SN74LV06A

SCES336J – MAY 2000 – REVISED JANUARY 2016

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Product Folder Links: SN54LV06A SN74LV06A

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Copyright © 2000–2016, Texas Instruments Incorporated

Typical Application (continued)

9.2.3 Application Curves

Figure 6. Output During Power Up with 4 k Pull-up at 3.3 V

10 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the

disturbance. For devices with a single supply, a 0.1

terminals then 0.01

μF or 0.022 μF capacitor is recommended for each power terminal. It is acceptable to parallel

multiple bypass capacitors to reject different frequencies of noise. 0.1

μF and 1 μF capacitors are commonly

used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best

results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices, inputs should not float.

In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two

inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be

left unconnected because the undefined voltages at the outside connections result in undefined operational

states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital

logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should

be applied to any particular unused input depends on the function of the device. Generally they will be tied to

part is a transceiver.

11.2 Layout Example

Figure 7. Layout Diagram