1

2

18

1Y1

1OE

1A1

4

16

1Y2

1A2

6

14

1Y3

1A3

8

12

1Y4

1A4

19

11

9

2Y1

2OE

2A1

13

7

2Y2

2A2

15

5

2Y3

2A3

17

3

2Y4

2A4

SN54LV240A, SN74LV240A

SCLS384I – SEPTEMBER 1997 – REVISED FEBRUARY 2015

www.ti.com

9 Detailed Description

9.1 Overview

The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory

address drivers, clock drivers, and bus-oriented receivers and transmitters.

These devices are organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE

is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in

the high-impedance state.

9.2 Functional Block Diagram

Figure 4. Logic Diagram (Positive Logic)

9.3 Feature Description

•

Wide operating voltage range operates from 2-V to 5.5-V operation

•

Allow down voltage translation inputs accept voltages to 5.5 V

•

10

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