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SN74LVC08APWG4 Datasheet(PDF) 5 Page - Texas Instruments |
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SN74LVC08APWG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 32 page SN54LVC08A, SN74LVC08A www.ti.com SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 Pin Functions (continued) PIN SOIC, SSOP, TYPE DESCRIPTION NAME SOP, CDIP, LCCC or TSSOP 1 5 7 NC(1) — — No connect 11 15 17 (1) NC – No internal connection 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage –0.5 6.5 V VI Input voltage(2) –0.5 6.5 V VO Output voltage(2)(3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCC or GND ±100 mA Ptot Power dissipation(4)(5) TA = –40°C to 125°C 500 mW TJ Junction temperature –65 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value of VCC is provided in the Recommended Operating Conditions table. (4) For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K. (5) For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K. 7.2 ESD Ratings VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22- ±1000 C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions for SN54LVC08A (1) SN54LVC08A –55°C to 125°C UNIT MIN MAX Operating 2 3.6 VCC Supply voltage V Data retention only 1.5 VIH High-level input voltage VCC = 2.7 V to 3.6 V 2 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. Copyright © 1993–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SN54LVC08A SN74LVC08A |
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