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SN74AHC595PWG4 Datasheet(PDF) 1 Page - Texas Instruments |
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SN74AHC595PWG4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 29 page 3D C3 1D C1 R 3D C3 2D C2 R 3D C3 2D C2 R 3D C3 2D C2 R 3D C3 2D C2 R 3D C3 2D C2 R 3D C3 2D C2 R 3D C3 2D C2 R 13 12 10 11 14 15 1 2 3 4 5 6 7 9 QA QB QC QD QE QF QG QH QH′ OE SRCLR RCLK SRCLK SER Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74AHC595 SCLS373K – MAY 1996 – REVISED SEPTEMBER 2015 SN74AHC595 8-Bit Shift Registers With 3-State Output Registers 1 Features 3 Description The SN74AHC595 device contains an 8-bit serial-in, 1 • Operating Range: 2-V to 5.5-V VCC parallel-out shift register that feeds an 8-bit D-type • 8-Bit Serial-In, Parallel-Out Shift storage register. The storage register has parallel 3- • Latch-Up Performance Exceeds 100 mA Per state outputs. Separate clocks are provided for both JESD 78, Class II the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, a serial • ESD Protection Exceeds JESD 22 (SER) input, and a serial output for cascading. When – 2000-V Human-Body Model (A114-A) the output-enable (OE) input is high, all outputs – 200-V Machine Model (A115-A) except QH ′ are in the high-impedance state. – 1000-V Charged-Device Model (C101) Device Information PART NUMBER PACKAGE BODY SIZE (NOM) 2 Applications SN74AHC595N PDIP (16) 19.31 mm × 6.35 mm • Network Switches SN74AHC595D SOIC (16) 9.90 mm × 3.90 mm • Power Infrastructures SN74AHC595DB SSOP (16) 6.20 mm × 5.30 mm • LED Displays SN74AHC595PW TSSOP (16) 5.00 mm × 4.40 mm • Servers (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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