Sup ply 1

0.1 F

Sup ply2

Sup ply 3

Vcc 3.3v

MCU

SN74LVC1G11

www.ti.com

SCES487G – SEPTEMBER 2003 – REVISED DECEMBER 2015

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Validate and test

the design implementation to confirm system functionality.

9.1 Application Information

The SN74LVC1G11 device offers logical AND configuration for many design applications. This example

describes basic power sequencing using the AND gate configuration. Power sequencing is often used in

applications that require a processor or other delicate device with specific voltage timing requirements in order to

protect the device from malfunctioning. In the application below, the power-good signals from the supplies tell the

MCU to continue an operation.

9.2 Typical Application

Figure 4. Typical Application Diagram

9.2.1 Design Requirements

•

Recommended input conditions:

–

For rise time and fall time specifications, see

Δt/Δv in the Recommended Operating Conditions table.

–

–

•

Recommended output conditions:

–

Load currents must not exceed ±50 mA.

•

Frequency selection criterion:

–

Figure 5 illustrates the effects of frequency on output current.

–

Added trace resistance and capacitance can reduce maximum frequency capability. Follow the layout

practices listed in the Layout section.

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