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VNQ7050AJ Datasheet(PDF) 25 Page - STMicroelectronics

Part # VNQ7050AJ
Description  Quad channel high-side driver with CurrentSense analog feedback
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

VNQ7050AJ Datasheet(HTML) 25 Page - STMicroelectronics

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VNQ7050AJ
Application information
4.1.1
Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7
kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12: "ISO 7637-2 -
electrical transient conduction along supply line".
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present
device only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns
automatically to normal operation after the test”.
Table 12: ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional performance
status
Minimum
number of
pulses or test
time
Burst cycle / pulse
repetition time
Pulse duration and
pulse generator
internal impedance
Level
US(1)
min
max
1
III
-112V
500 pulses
0,5 s
2ms, 10Ω
2a
III
+55V
500 pulses
0,2 s
5 s
50µs, 2Ω
3a
IV
-220V
1h
90 ms
100 ms
0.1µs, 50Ω
3b
IV
+150V
1h
90 ms
100 ms
0.1µs, 50Ω
4 (2)
IV
-7V
1 pulse
100ms, 0.01Ω
Load dump according to ISO 16750-2:2010
Test B (3)
40V
5 pulse
1 min
400ms, 2Ω
Notes:
(1)US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
(2)Test pulse from ISO 7637-2:2004(E).
(3)With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).
4.3
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.
DocID027405 Rev 1
25/42


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