List of figures

VNQ7050AJ

List of figures

Figure 1: Block diagram ..............................................................................................................................5

Figure 2: Configuration diagram (top view).................................................................................................6

Figure 3: Current and voltage conventions.................................................................................................7

Figure 4: Switching times and Pulse skew ...............................................................................................14

Figure 5: Current sense timings (current sense mode) ............................................................................14

Figure 6: TDSKON....................................................................................................................................15

Figure 7: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ........................16

Figure 8: Latch functionality - behavior in hard short circuit condition......................................................17

Figure 9: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) ......17

Figure 10: Standby mode activation .........................................................................................................18

Figure 11: Standby state diagram.............................................................................................................18

Figure 12: OFF-state output current .........................................................................................................19

Figure 13: Standby current .......................................................................................................................19

Figure 14: IGND(ON) vs Tcase ................................................................................................................19

Figure 15: Logic Input high level voltage ..................................................................................................19

Figure 16: Logic Input low level voltage....................................................................................................19

Figure 17: High level logic input current ...................................................................................................19

Figure 18: Low level logic input current ....................................................................................................20

Figure 19: Logic Input hysteresis voltage .................................................................................................20

Figure 20: FaultRST Input clamp voltage .................................................................................................20

Figure 21: Undervoltage shutdown...........................................................................................................20

Figure 22: On-state resistance vs Tcase ..................................................................................................20

Figure 23: On-state resistance vs VCC ....................................................................................................20

Figure 24: Turn-on voltage slope ..............................................................................................................21

Figure 25: Turn-off voltage slope ..............................................................................................................21

Figure 26: Won vs Tcase ..........................................................................................................................21

Figure 27: Woff vs Tcase ..........................................................................................................................21

Figure 28: ILIMH vs. Tcase.......................................................................................................................21

Figure 29: OFF-state open-load voltage detection threshold ...................................................................21

Figure 30: Vsense clamp vs. Tcase..........................................................................................................22

Figure 31: Vsenseh vs. Tcase ..................................................................................................................22

Figure 32: Application diagram .................................................................................................................24

Figure 33: Simplified internal structure .....................................................................................................24

Figure 34: CurrectSense and diagnostic – block diagram........................................................................26

Figure 35: CurrentSense block diagram ...................................................................................................27

Figure 36: Analogue HSD – open-load detection in off-state ...................................................................28

Figure 37: Open-load / short to VCC condition.........................................................................................29

Figure 38: Maximum turn off current versus inductance ..........................................................................31

Figure 39: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................32

Figure 40: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ...........................................32

Figure 41: Rthj-amb vs PCB copper area in open box free air condition (one channel on) .....................33

Figure 42: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) ..............33

Figure 43: Thermal fitting model of a double-channel HSD in PowerSSO-16..........................................34

Figure 44: PowerSSO-16 package dimensions........................................................................................35

Figure 45: PowerSSO-16 reel 13" ............................................................................................................37

Figure 46: PowerSSO-16 carrier tape ......................................................................................................38

Figure 47: PowerSSO-16 schematic drawing of leader and trailer tape ..................................................38

Figure 48: PowerSSO-16 marking information .........................................................................................39

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