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SN74LVC2G125DCUR Datasheet(PDF) 9 Page - Texas Instruments |
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SN74LVC2G125DCUR Datasheet(HTML) 9 Page - Texas Instruments |
9 / 22 page 1A 1Y 1 2A 2 2Y OE OE 9 SN74LVC2G125 www.ti.com SCES204P – APRIL 1999 – REVISED JANUARY 2016 Product Folder Links: SN74LVC2G125 Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The SN74LVC2G125 device contains dual buffer gate device with output enable control and performs the Boolean function Y = A. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 8.2 Functional Block Diagram 8.3 Feature Description • Wide operating voltage range – Operates from 1.65 V to 5.5 V • Allows down voltage translation • Inputs accept voltages to 5.5 V • Ioff Feature – Allows voltages on the inputs and outputs, when VCC is 0 V 8.4 Device Functional Modes Table 1. Function Table INPUTS OUTPUT Y OE A L H H L L L H X Z |
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