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54F377FM Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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54F377FM Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Connection Diagrams Pin Assignment for DIP SOIC and Flatpak TLF9525 – 2 Pin Assignment for LCC TLF9525 – 3 Unit LoadingFan Out 54F74F Pin Names Description UL Input IIH IIL HIGHLOW Output IOH IOL D0–D7 Data Inputs 1010 20 mA b06 mA CE Clock Enable (Active LOW) 1010 20 mA b06 mA CP Clock Pulse Input 1010 20 mA b06 mA Q0–Q7 Data Outputs 50333 b 1 mA20 mA Mode Select-Function Table Operating Mode Inputs Output CP CE Dn Qn Load ‘‘1’’ L Ih H Load ‘‘0’’ L II L Hold L h X No Change (Do Nothing) X H X No Change H e HIGH Voltage Level h e HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition L e LOW Voltage Level I e LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition X e Immaterial L e LOW-to-HIGH Clock Transition Logic Diagram TLF9525 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 |
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