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GS2960-IBE3 Datasheet(PDF) 6 Page - Semtech Corporation |
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GS2960-IBE3 Datasheet(HTML) 6 Page - Semtech Corporation |
6 / 97 page GS2960 3Gb/s, HD, SD SDI Receiver Complete with SMPTE Video Processing Data Sheet 48003 - 6 September 2012 6 of 97 List of Figures Figure 3-1: Digital Input Pin with Schmitt Trigger............................................................................... 23 Figure 3-2: Bidirectional Digital Input/Output Pin..............................................................................23 Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength ........ 24 Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 24 Figure 3-5: VBG .............................................................................................................................................. 24 Figure 3-6: LB_CONT .................................................................................................................................... 25 Figure 3-7: Loop Filter .................................................................................................................................. 25 Figure 3-8: SDI/SDI and TERM .................................................................................................................. 25 Figure 3-9: SDO/SDO .................................................................................................................................... 25 Figure 4-1: Level A Mapping ...................................................................................................................... 26 Figure 4-2: Level B Mapping ...................................................................................................................... 27 Figure 4-3: 27MHz Clock Sources ............................................................................................................ 30 Figure 4-4: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 33 Figure 4-5: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 34 Figure 4-6: PCLK to Data and Control Signal Output Timing - DDR Mode ................................. 35 Figure 4-7: DDR Video Interface .............................................................................................................. 38 Figure 4-8: Delay Adjustment Ranges .................................................................................................... 39 Figure 4-9: Switch Line Locking on a Non-Standard Switch Line ................................................. 41 Figure 4-10: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode .................................... 45 Figure 4-11: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode 3G Level B 20-bit Mode, each 10-bit stream ......................................................................................... 45 Figure 4-12: H:V:F Output Timing - 3G Level B 10-bit Mode .......................................................... 45 Figure 4-13: H:V:F Output Timing - HD 20-bit Output Mode ......................................................... 46 Figure 4-14: H:V:F Output Timing - HD 10-bit Output Mode ......................................................... 46 Figure 4-15: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 46 Figure 4-16: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 46 Figure 4-17: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 48 Figure 4-18: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 48 Figure 4-19: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 49 Figure 4-20: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 49 Figure 4-21: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 50 Figure 4-22: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 51 Figure 4-23: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16) .............................. 51 Figure 4-24: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31) .......................................... 52 Figure 4-25: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 52 Figure 4-26: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 53 Figure 4-27: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 53 Figure 4-28: Y/1ANC and C/2ANC Signal Timing .............................................................................. 62 Figure 4-29: Ancillary Data Extraction - Step A .................................................................................. 69 Figure 4-30: Ancillary Data Extraction - Step B ................................................................................... 70 Figure 4-31: Ancillary Data Extraction - Step C .................................................................................. 70 Figure 4-32: Ancillary Data Extraction - Step D .................................................................................. 71 Figure 4-33: GSPI Application Interface Connection ........................................................................ 73 Figure 4-34: Command Word Format ..................................................................................................... 74 Figure 4-35: Data Word Format ................................................................................................................ 74 Figure 4-36: Write Mode .............................................................................................................................. 75 Figure 4-37: Read Mode ............................................................................................................................... 75 Figure 4-38: GSPI Time Delay .................................................................................................................... 75 Figure 4-39: In-Circuit JTAG ...................................................................................................................... 90 Figure 4-40: System JTAG ........................................................................................................................... 90 Figure 4-41: Reset Pulse ............................................................................................................................... 91 Figure 7-1: Pb-free Solder Reflow Profile .............................................................................................. 96 |
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