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ISL78229ARZ Datasheet(PDF) 3 Page - Intersil Corporation |
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ISL78229ARZ Datasheet(HTML) 3 Page - Intersil Corporation |
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3 / 71 page  ISL78229 3 FN8656.3 February 12, 2016 Submit Document Feedback Pin Configuration ISL78229 (40 LD 6x6 WFQFN) TOP VIEW 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 BOOT1 UG1 PH1 LG1 PVCC PGND LG2 PH2 UG2 BOOT2 SLOPE FB COMP SS IMON TRACK ADDR1 ADDR2 PGOOD FSYNC PAD Functional Pin Description PIN NAME PIN # DESCRIPTION SLOPE 1 This pin programs the slope of the internal slope compensation. A resistor should be connected from the SLOPE pin to GND. Refer to “Adjustable Slope Compensation” on page 33 for how to select this resistor value. FB 2 The inverting input of the error amplifier for the voltage regulation loop. A resistor network must be placed between the FB pin and the output rail to set the boost converter’s output voltage. Refer to “Output Voltage Setting” on page 65 for more details. There are also output overvoltage and undervoltage comparators on this pin. Refer to “Output Undervoltage Fault” on page 35 and “Output Overvoltage Fault” on page 36 and for more details. COMP 3 The output of the transconductance error amplifier (Gm1) for the output voltage regulation loop. Place the compensation network between the COMP pin and ground. Refer to “Output Voltage Regulation Loop” on page 26 for more details. The COMP pin voltage can also be controlled by the constant current control loop error amplifier (Gm2) output through a diode ( DCC) when the constant current control loop is used to control the input average current. Refer to “Constant Current Control (CC)” on page 37 for more details. SS 4 A capacitor placed from SS to ground will set up the soft-start ramp rate and in turn determine the soft-start time. Refer to “Soft-Start” on page 31 for more details. |
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