AD9531 datasheet(2/88 Pages) AD

Part #	AD9531

Description	3-Channel Clock Generator, 24 Outputs

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AD9531

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

Conditions..................................................................................... 5

Supply Current.............................................................................. 5

Power Dissipation......................................................................... 6

LDET1/M1, LDET2/M2, LDET3/M3, and LOR/M4 Pins...... 8

REF1_SEL Pin............................................................................... 8

PLL1 Characteristics .................................................................... 8

PLL2 Characteristics .................................................................. 13

PLL3 Characteristics .................................................................. 17

Serial Control Port ..................................................................... 20

Absolute Maximum Ratings.......................................................... 21

ESD Caution................................................................................ 21

Pin Configuration and Function Descriptions........................... 22

Typical Performance Characteristics ........................................... 25

PLL1 Characteristics .................................................................. 25

PLL2 Characteristics .................................................................. 26

PLL3 Characteristics .................................................................. 27

General Characteristics ............................................................. 28

Terminology .................................................................................... 29

Theory of Operation ...................................................................... 30

PLL1—Integer/Fractional-N PLL ............................................ 30

PLL1 Loop Configurations........................................................ 31

PLL1 Reference Clock Inputs (REF1_Ax/REF1_Bx)............. 34

PLL1 Reference Frequency Scaling.......................................... 34

PLL1 Phase Frequency Detector (PFD) and Charge Pumps..... 35

PLL1 Loop Filter......................................................................... 35

PLL1 Internal VCO .................................................................... 35

PLL1 VCO Divider (M1)........................................................... 35

PLL1 External VCXO Input (RFIN1_x).................................. 35

PLL1 Clock Distribution ........................................................... 36

PLL1 Holdover Mode and Freerun Mode............................... 37

PLL1 Reference Selection—Manual and Automatic ............. 37

PLL1 Internal VCO Calibration ............................................... 38

PLL1 Σ-Δ Modulator.................................................................. 40

PLL1 Lock Detector ................................................................... 40

PLL2—Integer-N PLL................................................................ 41

PLL2 Reference Clock Input (REF2_P/REF2_N).................. 41

PLL2 Reference Divider (R2).................................................... 41

PLL2 PFD and Charge Pump ................................................... 41

PLL2 Loop Filter......................................................................... 42

PLL2 VCO................................................................................... 42

PLL2 VCO Divider (M2)........................................................... 44

PLL2 Feedback Divider (N2).................................................... 44

PLL2 Clock Distribution ........................................................... 44

PLL3 Integer-N PLL................................................................... 46

PLL3 Reference Clock Input (REF3_P/REF3_N).................. 46

PLL3 Input Frequency Scaling ................................................. 46

PLL3 PFD and Charge Pumps.................................................. 46

PLL3 Loop Filters....................................................................... 47

PLL3 VCOs ................................................................................. 47

PLL3 Feedback Dividers............................................................ 47

PLL3B Reference Divider (R3B) .............................................. 47

PLL3 Clock Distribution ........................................................... 47

Additional Features ........................................................................ 49

Power-On Reset (POR) ............................................................. 49

ROM Profiles .............................................................................. 49

Multifunction Pins (LDET1/M1, LDET2/M2, LDET3/M3,

LOR/M4) ..................................................................................... 49

Loss of Reference (LOR)............................................................ 50

PLL Lock Detection (LDETx) .................................................. 51

Automatic Output Synchronization ........................................ 51

Serial Control Port ......................................................................... 54

Serial Control Port Pin Descriptions....................................... 54

Operation of the Serial Control Port ....................................... 54

Instruction Word (16 Bits)........................................................ 55

MSB/LSB First Transfers ........................................................... 55

Register Map ................................................................................... 57

Register Map Details ...................................................................... 60

Serial Port Control Registers—Register 0x0000 to Register

0x0005.......................................................................................... 60

Device Identification and ROM Profile Registers—Register

0x000A to Register 0x000E ....................................................... 60

Status Registers—Register 0x0080 to Register 0x0082.......... 61

LDET/LOR Control Registers—Register 0x0083 to Register

0x0085.......................................................................................... 61

PLL1 Registers ............................................................................ 62

Rev. 0 | Page 2 of 88

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