SPI/MICROWIRE-Compatible

UART in QSOP-16

IRQ

N

RM MASK

TM MASK

PM MASK

TRANSITION ON RX

SHUTDOWN

RAM MASK

FRAMING ERROR

SHUTDOWN

RAM MASK

R

S

Q

R

NEW DATA AVAILABLE

DATA READ

TRANSMIT BUFFER EMPTY

DATA READ

PE = 1 AND RECEIVED PARITY BIT = 1

PE = 0 OR RECEIVED PARITY BIT = 0

T

Pr

RA

FE

R

S

Q

R

S

Q

Figure 6. Interrupt Sources and Masks Functional Diagram

Table 6. Interrupt Sources and Masks—Bit Descriptions

MEANING

WHEN SET

DESCRIPTION

Received parity bit = 1

Transition on RX when

in shutdown; framing

error when not in

shutdown

RA/FE

RAM

This is the RA (RX-transition) bit in shutdown, and the FE (framing-error) bit in

operating mode. RA is set if there has been a transition on RX since entering

shutdown. RA is cleared when the MAX3100 exits shutdown. IRQ is asserted

when RA is set and RAM = 1.

FE is determined solely by the currently received data, and is not stored in FIFO.

The FE bit is set if a zero is received when the first stop bit is expected. FE is

cleared upon receipt of the next properly framed character. IRQ is asserted

when FE is set and RAM = 1.

MASK

BIT

Pr

PM

The Pr bit reflects the value in the word currently in the receive-buffer register

(oldest data available). The Pr bit is set when parity is enabled (PE = 1) and the

received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PE

= 0), or when parity is enabled and the received bit is 0. An interrupt is issued

based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next

value that will be read by a Read Data operation.

BIT

NAME

Data available

R

RM

The R bit is set when new data is available to be read from the receive register/

FIFO. FIFO is cleared when all data has been read. An interrupt is asserted as long

as R = 1 and RM = 1.

Transmit buffer is

empty

T

TM

The T bit is set when the transmit buffer is ready to accept data. IRQ is asserted

low if TM = 1 and the transmit buffer becomes empty. This source is cleared on

CS’s rising edge during a Read Data operation. Although the interrupt is cleared,

T may be polled to determine transmit-buffer status.

Interrupt Sources and Masks

A Read Data operation clears the interrupt IRQ. Table

6 gives the details for each interrupt source. Figure 6

shows the functional diagram for the interrupt sources

and mask blocks.

MAX3100

Maxim Integrated

11

MAX3100