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ICS1524 Datasheet(HTML) 6 Page - Integrated Circuit Systems

Part No. ICS1524
Description  Dual Output Phase Controlled SSTL-3/PECL Clock Generator
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Maker  ICST [Integrated Circuit Systems]
Homepage  http://www.icst.com
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ICS1524 Datasheet(HTML) 6 Page - Integrated Circuit Systems

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ICS1524
6
ICS1524 Rev C 01/31/2003
Detailed Register Description
Name:
Input Control
Register:
0 h
Index:
Read / Write
Bit
Name
Description
0
PDen
RESERVED
1
PD_Pol
Input MUX Control
2
Ref_Pol
Phase/Frequency Detector External Reference Polarity —
Edge of input signal on which Phase Detector triggers.
0 = Rising Edge (default)
1 = Falling Edge
3
Fbk_Pol
External Reference Feedback Polarity — Edge of EXTFB (pin 6) signal on which
Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1).
0 = Positive Edge (default)
1 = Negative Edge
4
Fbk_Sel
External Feedback Select
0 = Internal Feedback (default)
1 = External Feedback
5
Func_Sel
Function Output Select — Selects re-clocked output to FUNC (pin 15).
0 = Recovered HSYNC (default). Regenerated HSYNC output.
1 = External HSYNC. Schmitt-trigger conditioned input from HSYNC (pin 7).
6
EnPLS
Enable LOCK/REF (pin14) Output
7
EnDLS
Bit Name Bit # Reset Value Description
PDen
0
1
Phase detector Enable
PD_Pol
1
0
Phase/Frequency Detector Input MUX Control
Ref_Pol
2
0
Phase/Frequency Detector External Reference Polarity
Fbk_Pol
3
0
External Reference Feedback Polarity
Fbk_Sel
4
0
External Feedback Select
Func_Sel
5
0
Function Output Select
EnPLS
6
1
Enable PLL Lock Status Output on LOCK/REF pin
EnDLS
7
0
Enable DPA Lock Status Output on LOCK/REF pin
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