OBSOLETE

54ACT573

SNOS141B – AUGUST 1998 – REVISED APRIL 2013

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Connection Diagrams

Figure 3. Pin Assignment for CDIP and CLGA

Figure 4. Pin Assignment for LCCC

Functional Description

The 'ACT573 contains eight D-type latches with Tri-State output buffers. When the Latch Enable (LE) input is

will change state each time its D input changes. When LE is LOW the latches store the information that was

present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The Tri-State buffers are

controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the

buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

TRUTH TABLE

(1)

Inputs

Outputs

OE

LE

D

L

H

H

H

L

H

L

L

L

L

X

H

X

X

Z

(1)

H = HIGH Voltage

L = LOW Voltage

Z = High Impedance

X = Immaterial

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

2

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