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KM681001A-15 Datasheet(PDF) 5 Page - Samsung semiconductor |
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KM681001A-15 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 9 page KM681001A CMOS SRAM PRELIMINARY Rev 5.0 - 5 - February 1998 WRITE CYCLE NOTE: tWR=tWR1, tWR2 Parameter Symbol KM681001A-15 KM681001A-20 Unit Min Max Min Max Write Cycle Time tWC 15 - 20 - ns Chip Select to End of Write tCW 10 - 12 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 10 - 12 - ns Write Pulse Width(OE High) tWP 10 - 12 - ns Write Pulse Width(OE Low) tWP1 15 - 20 - ns Write Recovery Time tWR* 0 - 0 - ns Write to Output High-Z tWHZ 0 8 0 10 ns Data to Write Time Overlap tDW 7 - 9 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 3 - 3 - ns Address Data Out Previous Valid Data Valid Data TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH) tAA tRC tOH |
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