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SP3238E Datasheet(PDF) 7 Page - Sipex Corporation |
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SP3238E Datasheet(HTML) 7 Page - Sipex Corporation |
7 / 14 page 7 Rev.4/08/02 SP3249E Intelligent +3.0V to +5.5V RS-232 Transceivers © Copyright 2002 Sipex Corporation Charge Pump The charge pump is a Sipex–patented design (U.S. #5,306,954) and uses a unique approach compared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages 5.5V regardless of the input voltage (V CC) over the +3.0V to +5.5V range. This is important to maintain compliant RS-232 levels regardless of power supply fluctuations. The charge pump operates in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V, the charge pump is enabled. If the output voltages exceed a magnitude of 5.5V, the charge pump is disabled. This oscillator controls the four phases of the voltage shifting (Figure 13). A descrip- tion of each phase follows. Phase 1 (Figure 11) — V SS charge storage — During this phase of the clock cycle, the positive side of capacitors C 1 and C2 are initially charged to VCC. C l + is then switched to GND and the charge in C 1 – is transferred to C 2 –. Since C 2 + is connected to V CC, the voltage potential across capacitor C2 is now 2 times V CC. Figure 7. Loopback Test Circuit for RS-232 Driver Data Transmission Rates Phase 2 (Figure 12) — V SS transfer — Phase two of the clock connects the negative terminal of C 2 to the VSS storage capacitor and the positive terminal of C 2 to GND. This transfers a negative generated voltage to C 3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C 3, the positive side of capacitor C1 is switched to V CC and the negative side is connected to GND. Phase 3 (Figure 14) Figure 8. Loopback Test Circuit Result at 120kbps (All Drivers Fully Loaded) Figure 9. Loopback Test Circuit result at 250kbps (All Drivers Fully Loaded) SP3249E TxIN TxOUT C1+ C1- C2+ C2- V+ V- VCC 0.1 µF 0.1 µF 0.1 µF + C2 C5 C1 + + C3 C4 + + 0.1 µF 0.1 µF LOGIC INPUTS VCC 5k Ω RxIN RxOUT LOGIC OUTPUTS GND 1000pF |
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