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74F573SMX Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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74F573SMX Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Unit LoadingFan Out 54F74F Pin Names Description UL Input IIH IIL HIGHLOW Output IOH IOL D0–D7 Data Inputs 1010 20 mA b06 mA LE Latch Enable Input (Active HIGH) 1010 20 mA b06 mA OE TRI-STATE Output Enable Input 1010 20 mA b06 mA (Active LOW) O0–O7 TRI-STATE Latch Outputs 15040(333) b 3 mA24 mA (20 mA) Functional Description The ’F573 contains eight D-type latches with 3-state output buffers When the Latch Enable (LE) input is HIGH data on the Dn inputs enters the latches In this condition the latch- es are transparent ie a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE The 3- state buffers are controlled by the Output Enable (OE) input When OE is LOW the buffers are in the bi-state mode When OE is HIGH the buffers are in the high impedance mode but this does not interfer with entering new data into the latches Function Table Inputs Outputs OE LE D O LH H H LH L L LL X O0 HX X Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial O0 e Value stored from previous clock cycle Logic Diagram TLF9566 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 |
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