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PE46120A-X Datasheet(PDF) 8 Page - Peregrine Semiconductor |
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PE46120A-X Datasheet(HTML) 8 Page - Peregrine Semiconductor |
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8 / 25 page  PE46120 Monolithic Phase & Amplitude Controller Page 8 DOC-54655-6 – (5/2015) www.psemi.com Programming Options Serial Interface The serial interface is a 14-bit serial-in shift register with two parallel-out channel registers RFOUT1 and RFOUT2 buffered by a transparent latch. The 14 bits are comprised of four bits defining the attenuation setting and five bits for the phase shift setting. Channel register RFOUT1 and RFOUT2 selection is determined by the value of the C0 bit contained as part of the 14-bit program word. The serial interface is controlled using three CMOS compatible signals: serial data in (SDI), clock (CLK) and latch enable (LE). The SDI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in starting with two spare bits first and then the phase setting LSB. The shift register must be loaded while LE is held LOW to prevent the internal channel register values from changing as data is entered. The LE input should then be toggled HIGH, latching the new data into the PE46120. SDO is a clock delayed reply of the user’s input SDI command for functional confirmation. Phase shift and attenuation setting truth tables are listed in Table 6 and –Table 7. The serial timing diagram is illustrated in Figure 2 and associated AC characteristics are listed in Table 10. Power-up Control Settings The PE46120 will power up in one of two default states depending upon the setting of the default state (DS) pin, as defined in Table 8 and Table 9. No specific signal sequencing is required for the default state to be set and active once VDD is applied. Figure 2 • Latched Buffered SDO Serial Interface SCLK SDI SDO Channel 1 Register Data Channel 2 Register Data LE S0 S1 P0 P1 P2 P3 P4 M0 M1 M2 M3 S2 S3 C0 01 S0 S1 P0 P1 P2 P3 P4 M0 M1 M2 M3 S2 S3 C0 S0 TOV TSCLK TSU TH TSCLKH TLCLKH TSettle TOH Default/Current Value Default/Current Value New Value New Value TSCLKL S1 P0 P1 P2 P3 P4 M0 M1 M2 M3 S2 S3 C0 S0 S1 P0 P1 P2 P3 P4 M0 M1 M2 M3 S2 S3 C0 |
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