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BQ27426YZFT Datasheet(PDF) 7 Page - Texas Instruments |
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BQ27426YZFT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 25 page  tSU(STA) SCL SDA tw(H) tw(L) tf tr t(BUF) tr td(STA) REPEATED START th(DAT) tsu(DAT) tf tsu(STOP) STOP START 7 bq27426 www.ti.com SLUSC91C – OCTOBER 2015 – REVISED FEBRUARY 2016 Product Folder Links: bq27426 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated I 2C-Compatible Interface Communication Timing Characteristics (continued) TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted) (Force Note1) (1) MIN NOM MAX UNIT (2) If the clock frequency (fSCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at 400 kHz. (See I2C Interface and I2C Command Waiting Time.) tw(H) SCL pulse duration (high) 4 μs tsu(STA) Setup for repeated start 4.7 μs tsu(DAT) Data setup time Host drives SDA 250 ns th(DAT) Data hold time Host drives SDA 0 ns tsu(STOP) Setup time for stop 4 μs t(BUF) Bus free time between stop and start Includes Command Waiting Time 66 μs tf SCL or SDA fall time(1) 300 ns tr SCL or SDA rise time(1) 300 ns fSCL Clock frequency(2) 100 kHz Fast Mode (400 kHz) td(STA) Start to first falling edge of SCL 600 ns tw(L) SCL pulse duration (low) 1300 ns tw(H) SCL pulse duration (high) 600 ns tsu(STA) Setup for repeated start 600 ns tsu(DAT) Data setup time Host drives SDA 100 ns th(DAT) Data hold time Host drives SDA 0 ns tsu(STOP) Setup time for stop 600 ns t(BUF) Bus free time between stop and start Includes Command Waiting Time 66 μs tf SCL or SDA fall time(1) 300 ns tr SCL or SDA rise time(1) 300 ns fSCL Clock frequency(2) 400 kHz Figure 1. I2C-Compatible Interface Timing Diagrams |
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