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CD4044BM Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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CD4044BM Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 6 page TLF5967 February 1988 CD4043BMCD4043BC Quad TRI-STATE NOR RS Latches CD4044BMCD4044BC Quad TRI-STATE NAND RS Latches General Description CD4043BMCD4043BC are quad cross-couple TRI-STATE CMOS NOR latches and CD4044BMCD4044BC are quad cross-couple TRI-STATE CMOS NAND latches Each latch has a separate Q output and individual SET and RESET inputs There is a common TRI-STATE ENABLE input for all four latches A logic ‘‘1’’ on the ENABLE input connects the latch states to the Q outputs A logic ‘‘0’’ on the ENABLE input disconnects the latch states from the Q outputs result- ing in an open circuit condition on the Q output The TRI-STATE feature allows common bussing of the outputs Features Y Wide supply voltage range 3V to 15V Y Low power 100 nW (typ) Y High noise immunity 045 VDD (typ) Y Separate SET and RESET inputs for each latch Y NOR and NAND configuration Y TRI-STATE output with common output enable Applications Y Multiple bus storage Y Strobed register Y Four bits of independent storage with output enable Y General digital logic Connection Diagrams CD4043BMCD4043BC Dual-In-Line and Flat Packages TLF5967 – 3 Top View CD4044BMCD4044BC Dual-In-Line and Flat Packages TLF5967 – 4 Top View Truth Table CD4043BMCD4043BC SRE Q XX 0OC 00 1 NC 10 1 1 01 1 0 11 1 D CD4044BMCD4044BC SRE Q XX 0 OC 111 NC 011 1 101 0 001 DD Order Number CD4043B or CD4044B OC TRI-STATE NC No change X Don’t care D Dominated by Se1 input DD Dominated by Re0 input C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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