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LM36923YFFR Datasheet(PDF) 6 Page - Texas Instruments |
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LM36923YFFR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 47 page t4 t2 t3 t5 t1 SCL SDA_IN SDA_OUT 6 LM36923H SNVSAF3A – FEBRUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Product Folder Links: LM36923H Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Electrical Characteristics (continued) Minimum and maximum limits apply over the full operating ambient temperature range ( −40°C ≤ TA ≤ 85°C), typical values are at TA = 25°C, and VIN = 3.6 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSTART-UP Turnon delay from shutdown to backlight on PWM input active, PWM = logic high,HWEN input from low to high, ƒPWM = 10 kHz (50% duty cycle) 3.5 5 ms PWMRES PWM input resolution 1.6 kHz ≤ ƒPWM ≤ 12 kHz, PWM hysteresis = 00, PWM sample rate = 11 11 bits VIH Input logic high HWEN, ASEL, SCL, SDA, PWM inputs 1.25 VIN V VIL Input logic low HWEN, ASEL, SCL, SDA, PWM inputs 0 0.4 tGLITCH PWM input glitch rejection PWM pulse filter = 00 0 15 ns PWM pulse filter = 01 60 100 140 PWM pulse filter = 10 90 150 210 PWM pulse filter = 11 120 200 280 tPWM_STBY PWM shutdown period Sample rate = 24 MHz 0.54 0.6 0.66 ms Sample rate = 4 MHz 2.7 3 3.3 Sample rate = 800 kHz 22.5 25 27.5 6.6 I 2C Timing Requirements See Figure 1 MIN MAX UNIT t1 SCL clock period 2.5 µs t2 Data in setup time to SCL high 100 ns t3 Data out stable after SCL low 0 ns t4 SDA low Setup Time to SCL low (start) 100 ns t5 SDA high hold time after SCL high (stop) 100 ns Figure 1. I2C Timing |
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