0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.2

0.4

0.6

0.8

1.0

3.3 V

TLV809K33

DSP, FPGA, ASIC

GND

GND

RESET

RESET

V

DD

3.3-V LDO

GND

OUT

IN

5 V

V

DD

9

TLV809

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SLVSA03D – JUNE 2010 – REVISED MARCH 2016

Product Folder Links: TLV809

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Copyright © 2010–2016, Texas Instruments Incorporated

9.2 Typical Application

Figure 10. Monitoring a 3.3-V Supply

9.2.1 Design Requirements

The device must ensure that the supply voltage does not drop more than 15% below 3.3 V. If the supply voltage

falls below 3.3 V – 15%, then the load must be disabled.

9.2.2 Detailed Design Procedure

9.2.3 Application Curve