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TLV809J25DBZT Datasheet(PDF) 9 Page - Texas Instruments |
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TLV809J25DBZT Datasheet(HTML) 9 Page - Texas Instruments |
9 / 20 page 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.2 0.4 0.6 0.8 1.0 VDD − Threshold Overdrive Voltage − V 3.3 V TLV809K33 DSP, FPGA, ASIC GND GND RESET RESET V DD 3.3-V LDO GND OUT IN 5 V V DD 9 TLV809 www.ti.com SLVSA03D – JUNE 2010 – REVISED MARCH 2016 Product Folder Links: TLV809 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated 9.2 Typical Application Figure 10. Monitoring a 3.3-V Supply 9.2.1 Design Requirements The device must ensure that the supply voltage does not drop more than 15% below 3.3 V. If the supply voltage falls below 3.3 V – 15%, then the load must be disabled. 9.2.2 Detailed Design Procedure The TLV809K33 is selected to ensure that VDD is greater than 2.87 V when the load is enabled. 9.2.3 Application Curve Figure 11. Minimum Pulse Duration at VDD vs VDD Threshold Overdrive Voltage |
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