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AD6649BCPZRL7 Datasheet(PDF) 8 Page - Analog Devices |
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AD6649BCPZRL7 Datasheet(HTML) 8 Page - Analog Devices |
8 / 40 page AD6649 Data Sheet Rev. C | Page 8 of 40 SWITCHING SPECIFICATIONS Table 4. Parameter Temperature Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 MHz Conversion Rate1 Full 40 250 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 4.0 ns CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Full 1.8 2.0 2.2 ns Divide-by-1 Mode, DCS Disabled Full 1.9 2.0 2.1 ns Divide-by-3 Through Divide-by-8 Modes, DCS Enabled Full 0.8 ns DATA OUTPUT PARAMETERS (DATA, OR) Data Propagation Delay (tPD) Full 6.0 ns DCO Propagation Delay (tDCO) Full 6.7 ns DCO-to-Data Skew (tSKEW) Full 0.4 0.7 1.0 ns Pipeline Delay—Fixed-Frequency NCO, 95 MHz FIR Filter (Latency) Full 23 Cycles Pipeline Delay—Tunable-Frequency NCO, 100 MHz FIR Filter (Latency) Full 43 Cycles Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms Wake-Up Time (from Standby) Full 10 µs Wake-Up Time (from Power-Down) Full 250 µs OUT-OF-RANGE RECOVERY TIME Full 3 Cycles 1 Conversion rate is the clock rate after the divider. |
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