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AD9628BCPZ-125 Datasheet(PDF) 1 Page - Analog Devices |
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AD9628BCPZ-125 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 42 page  12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet AD9628 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 1.8 V analog supply operation 1.8 V CMOS or LVDS outputs SNR = 71.2 dBFS @ 70 MHz SFDR = 93 dBc @ 70 MHz Low power: 101 mW/channel @ 125 MSPS Differential analog input with 650 MHz bandwidth IF sampling frequencies to 200 MHz On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.25 LSB Serial port control options Offset binary, Gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Hand-held scope meters Portable medical imaging Ultrasound Radar/LIDAR FUNCTIONAL BLOCK DIAGRAM VIN+A VIN–A VREF SENSE VCM RBIAS VIN–B VIN+B ORA D0A D11A DCOA DRVDD ORB D11B D0B DCOB SDIO AGND AVDD SCLK SPI PROGRAMMING DATA PDWN DFS CLK+ CLK– MODE CONTROLS DCS DUTY CYCLE STABILIZER SYNC DIVIDE 1 TO 8 OEB CSB REF SELECT ADC ADC AD9628 NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES. Figure 1. PRODUCT HIGHLIGHTS 1. The AD9628 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or LVDS logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. 3. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments. 4. The AD9628 is packaged in a 64-lead RoHS-compliant LFCSP that is pin compatible with the AD9650/AD9269/ AD9268 16-bit ADC, the AD9258/AD9251/AD9648 14-bit ADCs, the AD9231 12-bit ADC, and the AD9608/AD9204 10-bit ADCs, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. |
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