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ADUC7122 Datasheet(PDF) 5 Page - Analog Devices |
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ADUC7122 Datasheet(HTML) 5 Page - Analog Devices |
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5 / 96 page  Data Sheet ADuC7122 SPECIFICATIONS AVDD = IOVDD = 3.0 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = −10°C to +95°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments ADC CHANNEL SPECIFICATIONS Eight acquisition clocks and fADC/2 ADC Power-Up Time 5 μs DC Accuracy1, 2 Resolution 12 Bits Integral Nonlinearity ±0.6 ±2 LSB 2.5 V internal reference, not production tested for PADC0/PADC1 channels Differential Nonlinearity3, 4 ±0.5 +1.4/−0.99 LSB 2.5 V internal reference, gauranteed monotonic DC Code Distribution 1 LSB ADC input is a dc voltage ENDPOINT ERRORS5 Internally unbuffered channels Offset Error ±2 ±5 LSB Offset Error Match ±1 LSB Gain Error ±2 ±5 LSB Gain Error Match ±1 LSB DYNAMIC PERFORMANCE fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS internally unbuffered channels Signal-to-Noise Ratio (SNR) 69 dB Includes distortion and noise components Total Harmonic Distortion (THD) −78 dB Peak Harmonic or Spurious Noise −75 dB Channel-to-Channel Crosstalk −80 dB Measured on adjacent channels ANALOG INPUT Input Voltage Ranges Differential Mode VCM6 ± VREF/2 V See Table 35 and Table 36 Single-Ended Mode 0 to VREF V Buffer bypassed Single-Ended Mode 0.15 AVDD − 1.5 V Buffer enabled Leakage Current ±0.2 µA Input Capacitance 20 pF During ADC acquisition buffer bypassed Input Capacitance 20 pF During ADC acquisition buffer enabled PADC0 INPUT 28.3 kΩ resistor, PGA gain = 3; acquisition time = 6 µs, pseudo differential mode Full Scale Input Range 20 1000 µA Input Leakage at PADC0P4 0.15 2 nA Resolution 11 Bits 0.1% accuracy, 5 ppm external resistor for I to V Gain Error4 1 % Gain Drift4 50 ppm/°C Offset4 3 6 nA PGA offset not included Offset Drift4 30 60 pA/°C PADC0P Compliant Range 0.1 AVDD − 1.2 V PADC1 INPUT 53.5 kΩ resistor, PGA gain = 3; acquisition time = 6 µs, pseudo differential mode Full Scale Input Range 10.6 700 µA Input Leakage at PADC1P4 0.15 2 nA Resolution 11 Bits 0.1% accuracy, 5 ppm external resistor for I to V Gain Error4 1 % Gain Drift4 50 ppm/°C Offset4 3 6 nA PGA offset not included Offset Drift4 30 60 pA/°C PADC1P Compliant Range 0.1 AVDD − 1.2 V Rev. A | Page 5 of 96 |
Similar Part No. - ADUC7122_14 |
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Similar Description - ADUC7122_14 |
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