ADUC7124_14 datasheet(10/110 Pages) AD

Part #	ADUC7124

Description	Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler

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ADuC7124/ADuC7126

Data Sheet

Rev. D | Page 10 of 110

SDA (I/O)

tBUF

MSB

LSB

ACK

MSB

1

9

8

2–7

1

SCL (I)

PS

STOP

CONDITION

START

CONDITION

S(R)

REPEATED

START

tR

tF

tR

tH

tL

tDSU

tDHD

tRSU

tDHD

tDSU

tSHD

tPSU

Figure 2. I2C-Compatible Interface Timing

SPI Timing

Table 4. SPI Master Mode Timing (Phase Mode = 1)

Parameter

Description

Min

Typ

Max

Unit

tSL

SCLK low pulse width1

(SPIDIV + 1) × tUCLK

ns

tSH

SCLK high pulse width1

(SPIDIV + 1) × tUCLK

ns

tDAV

Data output valid after SCLK edge

25

ns

tDSU

Data input setup time before SCLK edge1

1 × tUCLK

ns

tDHD

Data input hold time after SCLK edge1

2 × tUCLK

ns

tDF

Data output fall time

5

12.5

ns

tDR

Data output rise time

5

12.5

ns

tSR

SCLK rise time

5

12.5

ns

tSF

SCLK fall time

5

12.5

ns

1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

MOSI

MSB

BIT 6 TO BIT 1

LSB

MISO

MSB IN

BIT 6 TO BIT 1

LSB IN

tSH

tSL

tSR

tSF

tDR

tDF

tDAV

tDSU

tDHD

Figure 3. SPI Master Mode Timing (Phase Mode = 1)

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