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TPS657095 Datasheet(PDF) 8 Page - Texas Instruments |
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TPS657095 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 41 page  tf tLOW tr thd;STA thd;DAT tsu;DAT tf HIGH tsu;STA S Sr P S thd;STA tr tBUF tsu;STO SDA SCL 8 TPS657095 SLVSCW2A – SEPTEMBER 2015 – REVISED FEBRUARY 2016 www.ti.com Product Folder Links: TPS657095 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated 6.6 Timing Requirements MIN MAX UNIT fMAX Clock frequency 400 kHz t(HIGH) Clock high time 600 ns t(LOW) Clock low time 1300 ns tr DATA and CLK rise time 300 ns tf DATA and CLK fall time 300 ns thd;STA Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns tsu;STA Setup time for repeated START condition 600 ns thd;DAT Data input hold time 10 ns tsu;DAT Data input setup time 100 ns tsu;STO STOP condition setup time 600 ns tBUF Bus free time 1300 ns Cl Load capacitance on SDA and SCL (with a 730 Ω or smaller pull-up resistor on SDA and SCL pulled up to 1.8V) 400 pF Figure 1. Serial I/f Timing Diagram |
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