OUT

V3

V2

V1

VSS

VDD

REG

PACK+

PACK±

RIN

C IN

RIN

C IN

RIN

C IN

CVD

R VD

V OV

8

9

1

3

4

5

6

PWPD

Enable

Active

Delay Charging/

Discharge circuit

Delay

Timer

+

-

Vref

+

-

Amp

Comp

UVP_Vref

Programmable

setting

V4

RIN

C IN

2

REG_EN

REG_EN

7

11

bq2961

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SLUSBU5A – MAY 2015 – REVISED JANUARY 2016

Product Folder Links: bq2961

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Copyright © 2015–2016, Texas Instruments Incorporated

Functional Block Diagram (continued)

Figure 10. bq2961xy Block Diagram

9.3 Feature Description

9.3.1 Pin Details

9.3.1.1 Input Sense Voltage, Vx

These inputs sense each battery cell voltage. A series resistor and a capacitor across the cell for each input is

required for noise filtering and stable voltage monitoring.

9.3.1.2 Output Drive, OUT

This terminal serves as the fault signal output in Active High.

9.3.1.3 Supply Input, VDD

This terminal is the unregulated input power source for the device. A series resistor is connected to limit the

current, and a capacitor is connected to ground for noise filtering.

9.3.1.4 Regulated Supply Output, REG

This terminal is connected to an external capacitor and provides a regulated supply to power a circuit such as a

Real Time Clock integrated circuit, or functions requiring a well-regulated supply. Maximum current load on this

pin cannot exceed 1 mA.