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TPS65835 Datasheet(PDF) 8 Page - Texas Instruments |
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TPS65835 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 67 page  TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 4.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT CHARGER / POWER PATH VVIN Voltage at charger input pin 3.7 28(1) V IVIN Input current at VIN pin 200 mA CVIN Capacitor on VIN pin 0.1 2.2 10 µF LVIN Inductance at VIN pin 0 2 µH VSYS Voltage at SYS pin 2.5 6.4 V ISYS(OUT) Output current at SYS pin 100 mA CSYS Capacitor on SYS pin 0.1 4.7 10 µF VBAT Voltage at BAT pin 2.5 6.4 V CBAT Capacitor on BAT pin 4.7 10 µF REXT(nCHG_STAT) Resistor connected to nCHG_STAT pin to limit current into pin 320 Ω BOOST CONVERTER / H-BRIDGE SWITCHES VIN(BST_SW) Input voltage for boost converter 2.5 6.5 V VBST_OUT Output voltage for boost converter 8 16 V CBST_OUT Boost output capacitor 3.3 4.7 10 µF LBST_SW (2) Inductor connected between SYS and BST_SW pins 4.7 10(3) µH LDO CVLDO External decoupling cap on pin VLDO 1 10 µF POWER MANAGEMENT CORE CONTROL (LOGIC LEVELS FOR GPIOs) VIL(PMIC) GPIO low level (BST_EN, CHG_EN, SW_SEL, VLDO_SET 0.4 V and to switch H-Bridge inputs to a low, 0, level) VIH(PMIC) GPIO high level (BST_EN, CHG_EN, SW_SEL, VLDO_SET 1.2 V and to switch H-Bridge inputs to a high, 1, level) (1) VIN pin has 28 V ESD protection (2) See Section 5.3.4 for information on boost converter inductor selection. (3) Design optimized for boost operation with 10 µH inductor 4.5 Thermal Information TPS65835 THERMAL METRIC RKP (VQFN) UNIT 40 PINS RθJA Junction-to-ambient thermal resistance(1) 38.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance(2) 26.5 °C/W RθJB Junction-to-board thermal resistance(3) 9.8 °C/W ψJT Junction-to-top characterization parameter(4) 0.3 °C/W ψJB Junction-to-board characterization parameter(5) 9.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance(6) 3.5 °C/W (1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer 8 Specifications Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 |
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