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TPS65835RKPT Datasheet(PDF) 6 Page - Texas Instruments |
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TPS65835RKPT Datasheet(HTML) 6 Page - Texas Instruments |
6 / 67 page TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Table 3-1. Pin Functions (continued) PIN I/O DESCRIPTION NO. NAME TEST/ Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST. 20 I SBWTCK Spy-Bi-Wire test clock input during programming and test P2.7/ General-purpose digital I/O pin 21 I/O XOUT Output terminal of crystal oscillator(3)) P2.6/ General-purpose digital I/O pin 24 XIN/ I/O XIN, Input terminal of crystal oscillator TA0.1 TA0.1, Timer0_A, compare: Out1 output 25 DVSS — MSP430 Ground reference(1) P1.1/ General-purpose digital I/O pin TA0.0/ Timer0_A, capture: CCI0A input, compare: Out0 output UCA0RXD/ USCI_A0 receive data input in UART mode 30 I/O UCA0SOMI/ USCI_A0 slave data out/master in SPI mode A1/ ADC10 analog input A1 CA1 Comparator_A+, CA1 input P1.2/ General-purpose digital I/O pin TA0.1/ Timer0_A, capture: CCI1A input, compare: Out1 output UCA0TXD/ USCI_A0 transmit data output in UART mode 31 I/O UCA0SIMO/ USCI_A0 slave data in/master out in SPI mode A2/ ADC10 analog input A2 CA2 Comparator_A+, CA2 input P1.3/ General-purpose digital I/O pin ADC10CLK/ ADC10, conversion clock output A3 ADC10 analog input A3 32 I/O VREF-/VEREF-/ ADC10 negative reference voltage CA3/ Comparator_A+, CA3 input CAOUT Comparator_A+, output P1.4/ General-purpose digital I/O pin SMCLK/ SMCLK signal output UCB0STE USCI_B0 slave transmit enable UCA0CLK/ USCI_A0 clock input/output 34 I/O A4 ADC10 analog input A4 VREF+/VEREF+/ ADC10 positive reference voltage CA4 Comparator_A+, CA4 input TCK JTAG test clock, input terminal for device programming and test P1.5/ General-purpose digital I/O pin TA0.0/ Timer0_A, compare: Out0 output UCB0CLK/ USCI_B0 clock input/output 39 UCA0STE/ I/O USCI_A0 slave transmit enable A5/ ADC10 analog input A5 CA5/ Comparator_A+, CA5 input TMS JTAG test mode select, input terminal for device programming and test MISCELLANEOUS AND PACKAGE All N/C pins are not connected internally (package to die). They should be connected to the main system 10, 40 N/C — ground. There is an internal electrical connection between the exposed thermal pad and the AGND ground pin of the device. The thermal pad must be connected to the same potential as the AGND pin on the printed 41 Thermal PAD — circuit board. Do not use the thermal pad as the primary ground input for the device. AGND pin must be connected to ground at all times. (3) If P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. 6 Terminal Configuration and Functions Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 |
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