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TPS650244RHBR Datasheet(PDF) 11 Page - Texas Instruments |
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TPS650244RHBR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 38 page TPS650240, TPS650241, TPS650242 TPS650243, TPS650244, TPS650245 www.ti.com SLVS774C – JUNE 2007 – REVISED JANUARY 2016 8.9 Electrical Characteristics: General VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TA = –40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VLDO1 AND VLDO2 LOW DROPOUT REGULATORS I(q) Operating quiescent current Current per LDO into VINLDO 16 30 μA I(SD) Shutdown current Total current into VINLDO, VLDO = 0 V 0.6 2 μA VINLDO Input voltage range for LDO1, LDO2 1.5 6.5 V VLDO1 LDO1 output voltage range 1 3.3 V VLDO2 LDO2 output voltage range 1 3.3 V VFB LDO1 and LDO2 feedback voltage See (2) 1 V IO Maximum output current for LDO1, LDO2 Vin = 1.8 V, Vo = 1.3 V 200 mA IO Maximum output current for LDO1, LDO2 Vin = 1.5 V; Vo = 1.3 V 120 mA ISC LDO1 & LDO2 short circuit current limit VLDO1 = GND, VLDO2 = GND 400 mA Minimum voltage drop at LDO1, LDO2 IO = 50 mA, VINLDO = 1.8 V 120 mV Minimum voltage drop at LDO1, LDO2 IO = 50 mA, VINLDO = 1.5 V 65 150 mV Minimum voltage drop at LDO1, LDO2 IO = 200 mA, VINLDO = 1.8 V 300 mV Output voltage ccuracy for LDO1, LDO2 IO = 10 mA –2% 1% VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5 Line regulation for LDO1, LDO2 –1% 1% V, IO = 10 mA Load regulation for LDO1, LDO2 IO = 0 mA to 200 mA –1% 1% Regulation time for LDO1, LDO2 Load change from 10% to 90% 10 μs Vdd_alive LOW DROPOUT REGULATOR Vdd_alive LDO output voltage, IO = 0 mA 1.2 TPS650240 to TPS650244 Vdd_alive V Vdd_alive LDO output voltage, IO = 0 mA 1.1 TPS650245 IO Output current for Vdd_alive 30 mA ISC Vdd_alive short circuit current limit Vdd_alive = GND 100 mA Output voltage accuracy for Vdd_alive IO = 0 mA –1% 1% Line regulation for Vdd_alive VCC = Vdd_alive + 0.5 V to 6.5 V, IO = 0 mA –1% 1% Regulation time for Vdd_alive Load change from 10% to 90% 10 μs ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3 VIH High level input voltage 1.3 VCC V VIL Low level input voltage 0 0.1 V IH Input bias current 0.001 0.05 μA THERMAL SHUTDOWN TSD Thermal shutdown Increasing junction temperature 160 °C Thermal shudown hysteresis Decreasing junction temperature 20 °C INTERNAL UNDER VOLTAGE LOCK OUT UVLO Internal UVLO VCC falling –3% 2.35 3% V VUVLO_HYST Internal UVLO comparator hysteresis 120 mV VOLTAGE DETECTOR COMPARATOR PWRFAIL_SNS Comparator threshold Falling threshold –2% 1 2% V Hysteresis 40 50 60 mV Propagation delay 25 mV overdrive 10 μs VOL Power fail output low voltage IOL = 5 mA 0.3 V (1) Typical values are at TA = 25°C (2) If the feedback voltage is forced higher than above 1.2 V, a leakage current into the feedback pin may occur. Copyright © 2007–2016, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS650240 TPS650241 TPS650242 TPS650243 TPS650244 TPS650245 |
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