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M21050G-14 Datasheet(PDF) 9 Page - M/A-COM Technology Solutions, Inc. |
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M21050G-14 Datasheet(HTML) 9 Page - M/A-COM Technology Solutions, Inc. |
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9 / 70 page  21050-DSH-001-F Mindspeed Technologies™ 1 Mindspeed Proprietary and Confidential 1.0 Functional Description 1.1 Detailed Feature Descriptions 1.1.1 Conventions Throughout this data sheet, physical pins will be denoted in bold italic print. An array of pins can be called by each individual pin name (e.g. MF0, MF1, MF2, MF3, and MF6) or as an array (e.g. MF [6,3:0]). The M21050 control is accessed through registers that employ an 8-bit address and an 8-bit data scheme. Registers are denoted in italic print, e.g. TestRegister and individual bits within the register will be called out as TestRegister [4:3] to denote the 4th and 3rd bit where bit 0 is the LSB and bit 7 is the MSB. Many features are bit mapped within a register; if the status of the other bits are uncertain, it is recommended that the user reads the value from the register before writing, to assure only the desired bits change. Writing in the same value to the bits within a register does not cause glitches to the unchanged features. The address for the register as well as its functions can be found in detail in Section 2.0. The purpose of the text description is to highlight the features of the register. For redundant items, such as the channel number, the registers will have a nomenclature of TestReg_0 for channel 0, TestReg_1 for channel 1. For general reference, the text will denote such registers as TestReg_N where N can vary from 0 to 7. 1.1.2 Reset Upon application of power, the M21050 automatically generates a master reset. At any time, forcing xRST = L causes the M21050 to enter the master reset state. A master reset can also be initiated through the registers in the two-wire interface control mode by writing AAh to Mastreset. Once a master reset is initiated, all registers are returned to the default values, the internal state machines cleared, and all CDR/BIST reset to the out-of-lock condi- tion. After a reset, the register Mastreset will automatically return to the default value of 00h. Each individual CDR can be soft reset by setting CDR_ctrlA_N[7] = 1 where N = 0 for CDR A0, N = 1 for CDR A1,…,N = 4 for CDR B0,...,N = 7 for CDR B3. The bit should be returned to 0b for normal operation. In this case, the registers that determine the CDR operation options such as data-rate, window sizes, etc., remain unchanged and only the CDR state-machine is reset, resulting in an out-of lock condition. 1.1.3 Internal Voltage Regulator The digital and analog core are designed to run at 1.2V, however, for operation from 1.8 to 2.5V, an internal linear voltage regulator is provided. xRegu_En = L enables the voltage regulator which uses AVdd_I/O and DVdd_I/O to generate the required 1.2V for AVdd_Core and DVdd_Core. In this mode, the AVdd_Core and DVdd_Core pins should be connected to a floating DC low inductance PCB plane, and AC bypassed to Vss using standard decou- pling techniques. If desired, AVdd_Core and DVdd_Core can be separated into individual planes. If 1.2V is avail- able, it can be connected directly to AVdd_Core and DVdd_Core, to save power, by bypassing the internal linear regulator with xRegu_En = H. In this case, it is recommended that the AVdd_Core and DVdd_Core pins be tied together to a common PCB plane, and bypassed to Vss with standard decoupling techniques. |
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