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TPS53315 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS53315 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 35 page TPS53315 SLUSAE6A – DECEMBER 2010 – REVISED DECEMBER 2015 www.ti.com Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. 29 31 N/C No connection 33 34 Open drain power good flag provides a 1-ms start up delay after the VFB pin voltage falls within specified PGOOD 32 O limits. When the VFB pin voltage goes outside the specified limits, the PGOOD pin goes low within 10 µs. 2 5 6 PGND 7 G Power GND 8 9 10 Switching frequency selection. Connect a resistance to GND or VREG to select switching frequency using RF 38 I Table 1. The switching frequency is detected and stored during the startup. OCL detection threshold setting pin, 10 µA at room temperature, 4700 ppm/°C current is sourced and set the OCL trip voltage as follows: TRIP 35 I space VOCL = VTRIP/8 (VTRIP ≤1.2 V, VOCL ≤ 150 mV) Supply input for high-side FET gate driver (boost terminal); connect capacitor from this pin to LL-node. VBST 30 P Internally connected to the VREG pin via bootstrap MOSFET switch. VDD 40 P Controller power supply input VFB 37 I Output feedback input; connect this pin to VOUT through a resistor divider. 11 12 VIN 13 P Conversion power input 14 15 VREG 3 P 5-V LDO output 4 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS53315 |
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