TPS92691, TPS92691-Q1

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SLVSD68 – DECEMBER 2015

6.4 Thermal Information

TPS92691/-Q1

PWP (HTSSOP)

UNIT

16 PINS

Junction-to-ambient thermal resistance

40.8

°C/W

Junction-to-case (top) thermal resistance

26.1

°C/W

Junction-to-board thermal resistance

22.2

°C/W

Junction-to-top characterization parameter

0.8

°C/W

Junction-to-board characterization parameter

22.0

°C/W

Junction-to-case (bottom) thermal resistance

2.3

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

on GATE and DDRV (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT VOLTAGE (VIN)

LDO dropout voltage

300

mV

BIAS SUPPLY (VCC)

Regulation voltage

No load

7.0

7.5

8.0

V

4.1

4.35

V

Supply undervoltage protection

3.75

4.0

V

Hysteresis

100

mV

Supply current limit

26

38

46

mA

Supply stand-by current

1.8

2.1

mA

Supply switching current

5.1

6.6

mA

OSCILLATOR (RT/SYNC)

165

200

230

kHz

Switching frequency

327

390

448

kHz

RT output voltage

1

V

SYNC rising threshold

2.7

3.1

V

SYNC falling threshold

1.8

2

V

Minimum SYNC clock pulse width

100

ns

GATE DRIVER (GATE)

Gate driver high side resistance

5.4

11.2

Ω

Gate driver low side resistance

4.3

10.5

Ω

CURRENT SENSE (IS)

Current limit threshold

497

525

550

mV

Leading edge blanking time

103

150

188

ns

Current limit fault time

35

µs

IS to GATE propagation delay

100

ns

PWM COMPARATOR AND SLOPE COMPENSATION

Maximum duty cycle

90.4%

93%

94.7%

IS to COMP level shift voltage

No slope compensation added

1.17

1.5

1.8

V

Slope compensation

200

mV

compensation)

IS level shift bias current

No slope compensation added

25

µA

(1)

All voltages are with respect to AGND unless otherwise noted

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