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BQ27546-G1 Datasheet(PDF) 7 Page - Texas Instruments |
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BQ27546-G1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 38 page  t(B) t(BR) t(HW1) t(HW0) t(CYCH) t(DW1) t(DW0) t(CYCD) Break 7-bit address 8-bit data (a) Break and Break Recovery (c) Host Transmitted Bit (d) Gauge Transmitted Bit (e) Gauge to Host Response 1.2V t(RISE) (b) HDQ line rise time 1-bit R/W t(RSPS) bq27546-G1 www.ti.com SLUSC53A – MAY 2015 – REVISED DECEMBER 2015 HDQ Communication Timing Characteristics (continued) TA = –40°C to 85°C, CREG = 0.47 μF, 2.45 V < VREGIN = VBAT < 5.5 V; typical values at TA = 25°C and VREGIN = VBAT = 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT t(DW1) bq27546-G1 sends 1 to host 32 50 μs t(HW0) Host sends 0 to bq27546-G1 86 145 μs t(DW0) bq27546-G1 sends 0 to host 80 145 μs t(RSPS) Response time, bq27546-G1 to host 190 950 μs t(B) Break time 190 μs t(BR) Break recovery time 40 μs t(RISE) HDQ line rising time to logic 1 (1.2 V) 950 ns 8.14 I 2C-Compatible Interface Timing Characteristics TA = –40°C to 85°C, CREG = 0.47 μF, 2.45 V < VREGIN = VBAT < 5.5 V; typical values at TA = 25°C and VREGIN = VBAT = 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tr SCL/SDA rise time 300 ns tf SCL/SDA fall time 300 ns tw(H) SCL pulse width (high) 600 ns tw(L) SCL pulse width (low) 1.3 μs tsu(STA) Setup for repeated start 600 ns td(STA) Start to first falling edge of SCL 600 ns tsu(DAT) Data setup time 1000 ns th(DAT) Data hold time 0 ns tsu(STOP) Setup time for stop 600 ns tBUF Bus free time between stop and start 66 μs fSCL Clock frequency (1) 400 kHz (1) If the clock frequency (fSCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at 400 kHz. (Refer to I2C Interface.) Figure 1. HDQ Timing Diagrams Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: bq27546-G1 |
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