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TPS549A20RVER Datasheet(PDF) 3 Page - Texas Instruments |
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TPS549A20RVER Datasheet(HTML) 3 Page - Texas Instruments |
3 / 47 page ADDR FB PGOOD GND EN MODE VBST VREG NC VDD SW NC SW VIN SW VIN SW VIN Thermal Pad 28 9 8 7 6 5 4 3 2 1 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 3 TPS549A20 www.ti.com SLUSC79A – NOVEMBER 2015 – REVISED DECEMBER 2015 Product Folder Links: TPS549A20 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated (1) I = Input, O = Output, P = Supply, G = Ground 5 Pin Configuration and Functions 28-PIN QFN (TOP VIEW) Pin Functions PIN I/O(1) DESCRIPTION NAME NO. ADDR 1 I PMBus address configuration pin. Connect this pin into a resistor divider between VREG and GND to program different address settings ALERT 26 O Alert output for the PMBus interface EN 3 I The enable pin turns on the DC-DC switching converter. FB 23 I VOUT feedback input. Connect this pin to a resistor divider between the VOUT pin and GND. GND 22 G This pin is the ground of internal analog circuitry and driver circuitry. Connect GND to the PGND plane with a short trace (For example, connect this pin to the thermal pad with a single trace and connect the thermal pad to PGND pins and PGND plane). MODE 21 I The MODE pin sets the forced continuous-conduction mode (FCCM) or auto-skip mode operation. It also selects the ramp coefficient of D-CAP3 mode. NC 5 — Not connected. These pins are floating internally. 18 PGND 10 G These ground pins are connected to the return of the internal low-side MOSFET. 11 12 13 14 PGOOD 2 O Open-drain power-good status signal which provides startup delay after the FB voltage falls within the specified limits. After the FB voltage moves outside the specified limits, PGOOD goes low within 2 µs. SCL 28 I Clock input for the PMBus interface SDA 27 I/O Data I/O for the PMBus interface |
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