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TPS22981RGPT Datasheet(PDF) 3 Page - Texas Instruments

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Part # TPS22981RGPT
Description  Thunderbolt Power Mux
Download  27 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS22981RGPT Datasheet(HTML) 3 Page - Texas Instruments

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V3P3
V3P3
V3P3OUT
S0
ENHVU
15
14
13
12
11
15
14
13
12
11
ENHVU
S0
V3P3OUT
V3P3
V3P3
TPS22981
www.ti.com
SLVSBM6B – DECEMBER 2012 – REVISED NOVEMBER 2015
5 Pin Configuration and Functions
RGP Package
RGP Package
VQFN With Exposed Thermal Pad
VQFN With Exposed Thermal Pad
Top View
Bottom View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
EN
5
I
Device active-high enable.
Enable VHV UVLO control of device enable. When asserted high, both V3P3 and VHV must be
ENHVU
16
I
present for device enable. When low, only V3P3 must be present for device enable.
Fault condition output. This pin is an open-drain pulldown indicating a fault condition. Place a pullup
FAULTZ
4
O
resistance (RFAULTZ) between this pin and V3P3. Float pin or tie pin to GND if unused.
1, 2, 3,
GND
P
Device ground. All GND pins must be connected to board ground.
13, 15
GND
EP
P
Exposed pad must be connected to device GND.
HV_EN
11
I
Active-high voltage output enable.
Sets the current limit for VHV in S0 mode. Place resistor between this pin and GND. See Equation 1 to
ISET_S0
10
I
calculate resistor value.
Sets the current limit for VHV in S3 mode. Place resistor between this pin and GND. See Equation 1 to
ISET_S3
9
I
calculate resistor value.
ISET_V3P
Sets the current limit for V3P3. Place resistor between this pin and GND. See Equation 1 to calculate
8
I
3
resistor value.
OUT
12, 14
O
Power output. Place a minimum of 1-µF capacitor to GND as close to this pin as possible.
S0
17
I
When this pin is asserted, the device is put in S0 mode. Otherwise the device operates in S3 mode.
3.3-V power supply input. Place a minimum of 0.1-µF capacitor to GND as close to this pin as
V3P3
19, 20
P
possible.
3.3-V bypass output. When ENHVU is low, this path is enabled by EN and the V3P3 UVLO. When
V3P3OUT
18
O
ENHVU is high, this path is enabled by EN and both the V3P3 UVLO and the VHV UVLO. Place a
minimum 0.1-uF capacitor to GND as close to this pin as possible.
VHV
6, 7
P
High voltage power supply input. See the Input Inductive Bounce section for more information.
Copyright © 2012–2015, Texas Instruments Incorporated
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