[AK8157A]

015002776-E-00

2015/03

- 11 -

9. Functional Descriptions

The AK8157A can generate MCLK, BCLK and LRCK simultaneously from 9.6MHz external input clock. It

requires operating the AK8157A with an audio device such as the AK4490, the AK4495 and so on. MCLK,

BCLK and LRCK phases are synchronized on a falling edge. (Figure 6).

CLKIN

9.6MHz

PLL1

PLL2

ODIV1

ODIV2

ODIV3

MCLK

BCLK

LRCK

Figure 6. System Clock Timing

The MCLK, BCLK and LRCK frequencies corresponding to each sampling speed can be selected by

MDSEL1-0 bits and MCKSEL1-0 bits (Table 1). Normal speed, double speed, quad speed and oct speed

modes are available with the AK8157A.

Table 1. Output Clock Configuration

MDSEL1-0 bits

MCKSEL1-0 bits

MCLK (MHz)

BCLK (MHz)

LRCK (kHz)

Sampling

Speed

64fs

fs

00

00

16.384

512fs

2.048

32

Normal

01

22.5792

2.8224

44.1

10 / 11

24.576

3.072

48

01

00

16.384

256fs

4.096

64

Double

01

22.5792

5.6448

88.2

10 / 11

24.576

6.144

96

10

00

16.384

128fs

8.192

128

Quad

01

22.5792

11.2896

176.4

10 / 11

24.576

12.288

192

11

00

16.384

64fs

16.384

256

Oct

01

22.5792

22.5792

352.8

10 / 11

24.576

24.576

384

The AK8157A should be reset once by bringing the RSTN

pin = “L” upon power-up. It initializes register

settings of the device.