Summary

TC90104FG

©2015 TOSHIBA CORPORATION

Page 10

Rev.1.00

2015/12/01

5.2.6

Output format

The output format (ITU-R BT.656/601) is selected by register FORMATO (Bank0, Sub address02h).

However, when D2 format is inputted, output format is fixed on 4:2:2 format.

Y: pedestal level = 16 LSB

C: center electric potential = 128 LSB

Signal process of Y output signal below pedestal is set by register CLP (Bank 0, Sub address 29h).

CLP = 1 : signal below pedestal is fixed on 16LSB

CLP = 0 : signal below pedestal is outputted through

Output signal

Bit

Data rate

Description

Y [0-7]

8

13.5 MHz/27 MHz

(ITU-R BT.601/656)

Y / YCbCr

(ITU-R BT.601/656)

C [0-7]

8

6.75 MHz

Cb / Cr

(CLK: 13.5 MHz)

CLK

1

13.5 MHz/27 MHz

864fH/1728fH: 625 line system

858fH/1716fH: 525 line system

Polarity: negative (initial setting)

HD

1

f H

Recovered horizontal sync signal

VD

1

f V

Recovered vertical sync signal

HD / VD pulse width in “Sync-through” mode

525i system

625i system

HD pulse width

4.74

μs

(128 cycle @ 27 MHz clock)

VD pulse width

3 .0 H

2.5 H or 3.0 H

*Notes

The HD pulse width used in ITU-R BT.656-compliant mode is the same as the zone defined from EAV to SAV.

If a non-standard signal is input during ITU-R BT.656-compliant mode, then the values may not necessarily be the

values shown in the above chart.

The VD pulse is synchronized using the HD standard. As a result, if the H cycle jitters, then the VD width will also

jitter.

Also, in Through mode, the phase with the HD has time lag of 0.5H in ODD/EVEN.