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TPS3711 Datasheet(PDF) 6 Page - Texas Instruments |
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TPS3711 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 23 page  VDD SENSE OUT VIT+ V HYS t pd(LH) t pd(LH) t pd(HL) VIT± t d(start) V(POR) TPS3711 SBVS272 – NOVEMBER 2015 www.ti.com 6.6 Timing Requirements PARAMETER TEST CONDITION MIN TYP MAX UNIT VDD = 24 V, ±10-mV input overdrive, tpd(HL) High-to-low propagation delay(1) 9.9 µs RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV VDD = 24 V, ±10-mV input overdrive, tpd(LH) Low-to-high propagation delay(1) 28.1 µs RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV td(start) (2) Startup delay VDD = 5 V 155 µs VDD = 12 V, 10-mV input overdrive, tr Output rise time 2.7 µs RL = 100 kΩ, CL = 10 pF, VO = (0.1 to 0.9) × VDD VDD = 12 V, 10-mV input overdrive, tf Output fall time 0.12 µs RL = 100 kΩ, CL = 10 pF, VO = (0.9 to 0.1) × VDD (1) High-to-low and low-to-high refers to the transition at the input pin (SENSE). (2) During power on, VDD must exceed 1.8 V for at least 150 µs (typ) before the output state reflects the input condition. Figure 1. Timing Diagram 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS3711 |
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