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TLC5925IDWR Datasheet(PDF) 7 Page - Texas Instruments |
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TLC5925IDWR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 28 page  TLC5925 www.ti.com SLVS765B – OCTOBER 2008 – REVISED SEPTEMBER 2015 6.8 Timing Requirements VDD = 3 V to 5.5 V (unless otherwise noted) MIN MAX UNIT tw(L) LE pulse duration 15 ns tw(CLK) CLK pulse duration 15 ns tw(OE) OE pulse duration 300 ns tsu(D) Setup time for SDI 3 ns th(D) Hold time for SDI 2 ns tsu(L) Setup time for LE 5 ns th(L) Hold time for LE 5 ns fCLK Clock frequency, Cascade operation 30 MHz 6.9 Switching Characteristics: VDD = 3 V VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH1 Low-to-high propagation delay time, CLK to OUTn 30 45 60 ns tPLH2 Low-to-high propagation delay time, LE to OUTn 30 45 60 ns tPLH3 Low-to-high propagation delay time, OE to OUTn 30 45 60 ns tPLH4 Low-to-high propagation delay time, CLK to SDO 30 40 ns tPHL1 High-to-low propagation delay time, CLK to OUTn 40 65 100 ns tPHL2 High-to-low propagation delay time, LE to OUTn 40 65 100 ns tPHL3 High-to-low propagation delay time, OE to OUTn 40 65 100 ns tPHL4 High-to-low propagation delay time, CLK to SDO 30 40 ns tw(CLK) Pulse duration, CLK 15 ns VIH = VDD, VIL = GND, tw(L) Pulse duration LE Rext = 840 Ω, VL = 4 V, 15 ns RL = 88 Ω, CL = 10 pF tw(OE) Pulse duration, OE 300 ns th(D) Hold time, SDI 2 ns tsu(D) Setup time, SDI 3 ns th(L) Hold time, LE 5 ns tsu(L) Setup time, LE 5 ns tr Rise time, CLK (1) 500 ns tf Fall time, CLK (1) 500 ns tor Rise time, outputs (off) 35 50 70 ns tof Rise time, outputs (on) 15 50 120 ns fCLK Clock frequency Cascade operation 30 MHz (1) If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TLC5925 |
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