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TPS650732RSLR Datasheet(PDF) 6 Page - Texas Instruments |
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TPS650732RSLR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 98 page  TPS65070, TPS65072 TPS65073, TPS650731, TPS650732 SLVS950H – JULY 2009 – REVISED SEPTEMBER 2015 www.ti.com Pin Functions (continued) PIN NO. I/O DESCRIPTION NAME TPS65072 TPS6507x SCLK 28 28 I Clock input for the I2C interface. SDAT 27 27 I/O Data line for the I2C interface. System voltage; output of the power path manager. All voltage regulators are typically powered from this SYS 7, 8 7, 8 O output. Temperature sense input. Connect to NTC thermistor to sense battery pack temperature. TPS6507x can be internally programmed to operate with a 10-k Ω curve 2 or 100-kΩ curve 1 thermistor. To linearize the TS 11 11 I thermistor response, use a 75-k Ω (for the 10-kΩ NTC) or a 360-kΩ (for the 100-kΩ NTC) in parallel with the thermistor. Default setting is 10-k Ω NTC. Input power for power path manager, connect to external voltage from a USB port. Connect external 1 µF USB 12 12 I (minimum) to GND. Default input current limit is 500 mA maximum. CONVERTERS AGND 42 42 — Analog GND, connect to PGND (thermal pad) DEFDCDC2 18 18 I Select Pin of DCDC2 output voltage. DEFDCDC3 17 17 I Select Pin of DCDC3 output voltage. EN_DCDC1 14 14 I Enable Input for DCDC1, active high EN_DCDC2 15 15 I Enable Input for DCDC2, active high EN_DCDC3 16 16 I Enable Input for DCDC3, active high TPS65072: This pin is the active high, push-pull output to enable an external LDO. This pin will be set and reset during startup and shutdown by the sequencing option programmed. The output is pulled internally to the SYS EN_EXTLDO — 39 O voltage if HIGH. The output is only used for sequencing options for Sirf Prima or Atlas 4 processors with DCDC_SQ[2..0] = 100 or DCDC_SQ[2..0] = 111. TPS65072, : This pin is the actively high enable input for the wLED driver. The wLED converter is enabled by EN_wLED — 47 I the ENABLE ISINK Bit OR enable EN_wLED pin. FB_WLED 38 38 I Feedback input for the boost converter's output voltage. Connect a resistor from this pin to GND to set the full scale current for Isink1 and Isink2 with Bit Current Level ISET1 in register WLED_CTRL0 set to 1. 35 35 I (AD_IN6) Analog input6 for the A/D converter. Connect a resistor from this pin to GND to set the full scale current for Isink1 and Isink2 with Bit Current Level ISET2 in register WLED_CTRL0 set to 0. 36 36 I (AD_IN7) Analog input7 for the A/D converter. ISINK1 34 34 I Input to the current sink 1. Connect the cathode of the LEDs to this pin. ISINK2 33 33 I Input to the current sink 2. Connect the cathode of the LEDs to this pin. L1 20 20 O Switch Pin for DCDC1. Connect to Inductor L2 22 22 O Switch Pin of DCDC2. Connect to Inductor. L3 31 31 O Switch Pin of DCDC3. Connect to Inductor. L4 37 37 I Switch Pin of the white LED (wLED) boost converter. Connect to Inductor and rectifier diode. Enable input for TPS6507x. When pulled LOW, the DCDC converters and LDOs start with the sequencing as PB_IN 25 25 I programmed internally. Internal 50kO pullup resistor to AVDD6 Open-drain output. This pin is driven by the status of the /PB_IN input (after debounce). PB_OUT=LOW if PB_OUT 24 24 O PB_IN=LOW PGND3 30 30 — Power GND for DCDC3. Connect to PGND (thermal pad) Open-drain power good output. The delay time equals the setting for Reset. The pin will go low depending on PGOOD 26 26 O the setting in register PGOODMASK. Optionally it is also driven LOW for 0.5 ms when PB_IN is pulled LOW for >15s. Power_ON input for the internal state machine. After PB_IN was pulled LOW to turn on the TPS6507x, the POWER_ON pin needs to be pulled HIGH by the application processor to keep the system in ON-state when POWER_ON 13 13 I PB_IN is released HIGH. If POWER_ON is released LOW, the DCDC converters and LDOs will turn off when PB_IN is HIGH. TPS65070, TPS65073, TPS650731, TPS650732: RESET 39 — O Open-drain active low reset output, reset delay time equals settings in register PGOOD. The status depends on the voltage applied at THRESHOLD. TPS65070, TPS65073, TPS650731, TPS650732:Input for the reset comparator. RESET will be LOW if this THRESHOLD 47 — I voltage drops below 1 V. Feedback voltage sense input. For the fixed voltage option, this pin must directly be connected to Vout1, for VDCDC1 19 19 I the adjustable version, this pin is connected to an external resistor divider. VDCDC2 23 23 I Feedback voltage sense input, connect directly to Vout2 6 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: TPS65070 TPS65072 TPS65073 TPS650731 TPS650732 |
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