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ADC08831 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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ADC08831 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 23 page Electrical Characteristics (Continued) The following specifications apply for V CC = VREF = +5VDC, and fCLK = 2 MHz unless otherwise specified. Boldface limits apply for T A = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) DC CHARACTERISTICS I CC Supply Current ADC08831 CLK = V CC CS = V CC 0.6 1.0 mA (max) CS = LOW 1.7 2.4 mA (max) I CC Supply Current ADC08832 CLK = V CC (Note 16) CS = V CC 1.3 1.8 mA (max) CS = LOW 2.4 3.5 mA (max) Electrical Characteristics The following specifications apply for V CC = VREF = +5 VDC, and tr = tf = 20 ns unless otherwise specified. Boldface limits apply for T A = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) f CLK Clock Frequency 2 MHz (max) Clock Duty Cycle (Note 14) 40 60 % (min) % (max) T C Conversion Time (Not Including MUX Addressing Time) f CLK = 2MHz 8 4 1/f CLK (max) µs (max) t CA Acquisition Time 1 ⁄2 1/f CLK (max) t SET-UP CS Falling Edge or Data Input Valid to CLK Rising Edge 25 ns (min) t HOLD Data Input Valid after CLK Rising Edge 20 ns (min) t pd1,tpd0 CLK Falling Edge to Output Data Valid (Note 15) C L = 100 pF: Data MSB First Data LSB First 250 200 ns (max) ns (max) t 1H,t0H TRI-STATE Delay from Rising Edge of CS to Data Output and SARS Hi-Z C L = 10 pF, RL = 10 kΩ (see TRI-STATE Test Circuits) 50 ns C L = 100 pF, RL = 2kΩ 180 ns (max) C IN Capacitance of Analog Input (Note 17) 13 pF C IN Capacitance of Logic Inputs 5 pF C OUT Capacitance of Logic Outputs 5 pF www.national.com 4 |
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