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AM3874BCYE80 Datasheet(PDF) 1 Page - Texas Instruments |
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AM3874BCYE80 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 358 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community AM3874, AM3871 SPRS695D – SEPTEMBER 2011 – REVISED JANUARY 2016 AM387x Sitara™ARM® Processors 1 High-Performance System-on-Chip (SoC) 1.1 Features 1 – Composite or S-Video Analog Output • High-Performance Sitara™ ARM® Processors – Macrovision® Support Available • ARM Cortex®-A8 Core – Digital HDMI 1.3 Transmitter With Integrated – ARMv7 Architecture PHY • In-Order, Dual-Issue, Superscalar Processor – Advanced Video Processing Features Such as Core Scan, Format, Rate Conversion • Neon™ Multimedia Architecture – Three Graphics Layers and Compositors • Supports Integer and Floating Point • Dual 32-Bit DDR2/DDR3 SDRAM Interfaces • Jazelle® RCT Execution Environment – Supports up to DDR2-800 and DDR3-1066 • ARM Cortex-A8 Memory Architecture – Up to Eight x 8 Devices Comprise 2GB of the – 32KB of Instruction and Data Caches Total Address Space – 512KB of L2 Cache – Dynamic Memory Manager (DMM) – 64KB of RAM, 48KB of Boot ROM • Programmable Multizone Memory Mapping • 128KB of On-Chip Memory Controller (OCMC) and Interleaving RAM • Enables Efficient 2D Block Accesses • Imaging Subsystem (ISS) • Supports Tiled Objects in 0°, 90°, 180°, or – Camera Sensor Connection 270° Orientation and Mirroring • Parallel Connection for Raw (up to 16-Bit) • Optimizes Interlaced Accesses and BT.656 or BT.1120 (8- and 16-Bit) • General-Purpose Memory Controller (GPMC) – Image Sensor Interface (ISIF) for Handling – 8- or 16-Bit Multiplexed Address and Data Bus Image and Video Data From the Camera – 512MB of Address Space Divided Among up to Sensor 8 Chip Selects – Resizer – Glueless Interface to NOR Flash, NAND Flash • Resizing Image and Video From 1/16x to 8x (BCH/Hamming Error Code Detection), SRAM • Generating Two Different Resizing Outputs and Pseudo-SRAM Concurrently – Error Locator Module (ELM) Outside of GPMC • Media Controller to Provide up to 16-Bit or 512-Byte Hardware – Controls the HDVPSS and ISS ECC for NAND • SGX530 3D Graphics Engine – Flexible Asynchronous Protocol Control for – Delivers up to 25 MPoly/sec Interface to FPGA, CPLD, ASICs, and so Forth – Universal Scalable Shader Engine (USSE™) • Enhanced Direct Memory Access (EDMA) – Direct3D™ Mobile, OpenGLES 1.1 and 2.0, Controller OpenVG™ 1.0, OpenMax™ API Support – Four Transfer Controllers – Advanced Geometry DMA-Driven Operation – 64 Independent DMA Channels and 8 – Programmable HQ Image Anti-Aliasing Independent QDMA Channels • Endianness • Dual-Port Ethernet (10/100/1000 Mbps) With Optional Switch – ARM Instructions and Data – Little Endian – IEEE 802.3 Compliant (3.3-V I/O Only) • HD Video Processing Subsystem (HDVPSS) – MII/RMII/GMII/RGMII Media Independent – Two 165-MHz, 2-channel HD Video Capture Interfaces Modules – Management Data I/O (MDIO) Module • One 16- or 24-Bit Input or Dual 8-Bit SD Input Channels – Reset Isolation • One 8-, 16-, or 24-Bit Input and One 8-Bit – IEEE 1588 Time-Stamping and Industrial Only Input Channels Ethernet Protocols – Two 165-MHz HD Video Display Outputs • Dual USB 2.0 Ports With Integrated PHYs • One 16-, 24-, or 30-Bit Output and One 16- – USB2.0 High- and Full-Speed Clients or 24-Bit Output – USB2.0 High-, Full-, and Low-Speed Hosts, or 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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