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TMS320C6655CZH25 Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320C6655CZH25 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 245 page  TMS320C6655, TMS320C6657 SPRS814B – MARCH 2012 – REVISED APRIL 2015 www.ti.com The .L and .S units can now support up to 64-bit operands. This allows for new versions of many of the arithmetic, logical, and data packing instructions to allow for more parallel operations per cycle. Additional instructions were added yielding performance enhancements of the floating point addition and subtraction instructions, including the ability to perform one double precision addition or subtraction per cycle. Conversion to/from integer and single-precision values can now be done on both .L and .S units on the C66x. Also, by taking advantage of the larger operands, instructions were also added to double the number of these conversions that can be done. The .L unit also has additional instructions for logical AND and OR instructions, as well as, 90 degree or 270 degree rotation of complex numbers (up to two per cycle). Instructions have also been added that allow for the computing the conjugate of a complex number. The MFENCE instruction is a new instruction introduced on the C66x DSP. This instruction will create a DSP stall until the completion of all the DSP-triggered memory transactions, including: • Cache line fills • Writes from L1D to L2 or from the CorePac to MSMC and/or other system endpoints • Victim write backs • Block or global coherence operations • Cache mode changes • Outstanding XMC prefetch requests This is useful as a simple mechanism for programs to wait for these requests to reach their endpoint. It also provides ordering guarantees for writes arriving at a single endpoint via multiple paths, multiprocessor algorithms that depend on ordering, and manual coherence operations. For more details on the C66x DSP and its enhancements over the C64x+ and C674x architectures, see the following documents: • C66x CPU and Instruction Set Reference Guide (SPRUGH7). • C66x DSP Cache User's Guide (SPRUGY8). • C66x CorePac User's Guide (SPRUGW0). Figure 3-1 shows the DSP core functional units and data paths. 8 Device Overview Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
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