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TMS320C6655CZHA Datasheet(PDF) 2 Page - Texas Instruments

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Part # TMS320C6655CZHA
Description  Fixed and Floating-Point Digital Signal Processor
Download  245 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320C6655CZHA Datasheet(HTML) 2 Page - Texas Instruments

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TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
www.ti.com
HyperLink provides a 40-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its low-
protocol
overhead
and
high
throughput
make
HyperLink
an
ideal
interface
for
chip-to-chip
interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices
transparently and executes tasks as if they are running on local resources.
1.3
Trademarks
All trademarks are the property of their respective owners.
1.4
Device Description
The C665x DSP is a highest-performance fixed/floating-point DSP that is based on TI's KeyStone
multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core
speed of up to 1.25 GHz. For developers of a broad range of applications, such as mission critical,
medical imaging, test and automation, and other applications requiring high performance, TI's C665x DSP
offers up to 2.5 GHz cumulative DSP and enables a platform that is power-efficient and easy to use. In
addition, it is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.
TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores,
memory subsystem, peripherals, and accelerators) and uses several innovative components and
techniques to maximize intra-device and inter-device communication that allows the various DSP
resources to operate efficiently and seamlessly. Central to this architecture are key components such as
Multicore Navigator that allows for efficient data management between the various device components.
The TeraNet is a non-blocking switch fabric enabling fast and contention-free internal data movement. The
multicore shared memory controller allows access to shared and external memory directly without drawing
from switch fabric capacity.
For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In
addition, the C66x core integrates floating point capability and the per core raw computational
performance is an industry-leading 40 GMACS/core and 20 GFLOPS/core (@1.25 GHz operating
frequency). It can execute 8 single precision floating point MAC operations per cycle and can perform
double- and mixed-precision operations and is IEEE754 compliant. The C66x core incorporates 90 new
instructions (compared to the C64x+ core) targeted for floating point and vector math oriented processing.
These enhancements yield sizeable performance improvements in popular DSP kernels used in signal
processing, mathematical, and image acquisition functions. The C66x core is backwards code compatible
with TI's previous generation C6000 fixed and floating point DSP cores, ensuring software portability and
shortened software development cycles for applications migrating to faster hardware.
The C665x DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and
data cache, there is 1024KB of dedicated memory per core that can be configured as mapped RAM or
cache. The device also integrates 1024KB of Multicore Shared Memory that can be used as a shared L2
SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast
access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running
at 1333 MHz and has ECC DRAM support.
This family supports a number of high speed standard interfaces including RapidIO ver 2, PCI Express
Gen2, and Gigabit Ethernet. It also includes I2C, UART, Multichannel Buffered Serial Port (McBSP),
Universal Parallel Port, and a 16-bit asynchronous EMIF, along with general purpose CMOS IO. For high
throughput, low latency communication between devices or with an FPGA, a 40-Gbaud full-duplex
interface called HyperLink is included.
The C665x device has a complete set of development tools, which includes: an enhanced C compiler, an
assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for
visibility into source code execution.
2
C665x Features and Description
Copyright © 2012–2015, Texas Instruments Incorporated
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