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TMS320C5545AZQWA06 Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320C5545AZQWA06 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 128 page  10 TMS320C5545 SPRS853C – JULY 2013 – REVISED MARCH 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320C5545 Terminal Configuration and Functions Copyright © 2013–2016, Texas Instruments Incorporated (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus-holder (2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive I/O-supply current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins. (3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where external pullup and pulldown resistors are required, see Section 6.8.1, Pullup and Pulldown Resistors. (4) Specifies the operating I/O supply voltage for each signal 4.2 Terminal Functions For proper device operation, external pullup and pulldown resistors may be required on some pins. Section 6.8.1, Pullup and Pulldown Resistors, discusses situations where external pullup and pulldown resistors are required. 4.2.1 Oscillator and PLL Terminal Functions Table 4-1 identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors or bus-holders, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed and shared pins, and debugging considerations, see Section 6, Device Configuration. Table 4-1. Oscillator and PLL Terminal Functions SIGNAL TYPE (1) (2) OTHER(3) (4) DESCRIPTION NAME NO. CLKOUT C12 O/Z – DVDDIO BH DSP clock output signal. For debug purposes only, the CLKOUT pin can be used to tap different clocks within the system clock generator. The SRC bits in the CLKOUT Control Source Register (CCSSR) can be used to specify the source of the CLKOUT pin. Additionally, the slew rate of the CLKOUT pin can be controlled by the Output Slew Rate Control Register (OSRCR) [1C16h]. The CLKOUT pin is enabled and disabled through the CLKOFF bit in the CPU ST3_55 register. When disabled, the CLKOUT pin is placed in high-impedance (Hi-Z). At reset the CLKOUT pin is enabled until the beginning of the boot sequence, when the on-chip bootloader sets CLKOFF = 1 and the CLKOUT pin is disabled (Hi-Z). For more information on the ST3_55 register, see the TMS320C55x 3.0 CPU Reference Guide (SWPU073). Note: This pin may consume static power if configured as Hi-Z and not externally pulled low or high. Prevent current drain by externally terminating the pin. CLKIN E12 I – DVDDIO BH Input clock. This signal is used to input an external clock when the 32-kHz on-chip oscillator is not used as the DSP clock (pin CLK_SEL = 1). For boot purposes, the CLKIN frequency is assumed to be either 11.2896, 12, or 12.288 MHz. The CLK_SEL pin (D12) selects between the 32-kHz crystal clock or CLKIN. When the CLK_SEL pin is low, this pin must be tied to ground (VSS). When CLK_SEL is high, this pin must be driven by an external clock source. If CLK_SEL is high, this pin is used as the reference clock for the clock generator. During bootup, the bootloader bypasses the PLL and assumes the CLKIN frequency is one of the following frequencies: 11.2896, 12, or 12.288 MHz. In addition, the bootloader sets the SPI clock rate at 500 kHz and the I2C clock rate at 400 kHz . CLK_SEL D12 I – DVDDIO BH Clock input select. This pin selects between the 32-kHz crystal clock or CLKIN. 0 = 32-kHz on-chip oscillator drives the RTC timer and the system clock generator while CLKIN is ignored. 1 = CLKIN drives the system clock generator and the 32-kHz on-chip oscillator drives only the RTC timer. This pin is not allowed to change during device operation; it must be tied high or low at the board. VDDA_PLL E10 PWR See Section 5.3, Recommended Operating Conditions 1.3-V analog PLL power supply for the system clock generator (PLLOUT ≤ 100 MHz). This signal can be powered from the ANA_LDOO pin. |
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