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TMS320C6655SCZH Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320C6655SCZH Datasheet(HTML) 1 Page - Texas Instruments |
1 / 245 page Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS320C6655, TMS320C6657 SPRS814B – MARCH 2012 – REVISED APRIL 2015 TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor 1 C665x Features and Description 1.1 Features 1 – HyperLink • One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With • Supports Connections to Other KeyStone Architecture Devices Providing Resource – 850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz Scalability C66x Fixed/Floating-Point CPU Core • Supports up to 40 Gbaud • 40 GMAC/Core for Fixed Point @ 1.25 GHz – Gigabit Ethernet (GbE) Subsystem • 20 GFLOP/Core for Floating Point @ 1.25 GHz • One SGMII Port • Multicore Shared Memory Controller (MSMC) • Supports 10/100/1000 Mbps Operation – 1024KB MSM SRAM Memory – 32-Bit DDR3 Interface (Shared by Two DSP C66x CorePacs for • DDR3-1333 C6657) • 8G Byte Addressable Memory Space – Memory Protection Unit for Both MSM SRAM – 16-Bit EMIF and DDR3_EMIF – Universal Parallel Port • Multicore Navigator • Two Channels of 8 bits or 16 bits Each – 8192 Multipurpose Hardware Queues with • Supports SDR and DDR Transfers Queue Manager – Two UART Interfaces – Packet-Based DMA for Zero-Overhead – Two Multichannel Buffered Serial Ports Transfers (McBSP) • Hardware Accelerators – I2C Interface – Two Viterbi Coprocessors – 32 GPIO Pins – One Turbo Coprocessor Decoder – SPI Interface • Peripherals – Semaphore Module – Four Lanes of SRIO 2.1 – Eight 64-Bit Timers • 1.24/2.5/3.125/5 GBaud Operation – Two On-Chip PLLs Supported Per Lane • Commercial Temperature: • Supports Direct I/O, Message Passing – 0°C to 85°C • Supports Four 1×, Two 2×, One 4×, and Two • Extended Temperature: 1× + One 2× Link Configurations – - 40°C to 100°C – PCIe Gen2 • Extended Low Temperature: • Single Port Supporting 1 or 2 Lanes – - 55°C to 100°C • Supports Up To 5 GBaud Per Lane 1.2 KeyStone Architecture TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink. Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by memory access. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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